SCSC2003 Abstract S1478
Identifying Equivalence of DEVSs: A Language Approach
Identifying Equivalence of DEVSs: A Language Approach
Submitting Author: Dr. Moon Hwang
Abstract:
Logical Analysis functionality should be required in the
system design and implementation process even if we use a system
theory approach. This paper presents a way of untimed analysis for
a discrete event system specification(DEVS) models with a language
approach. Firstly, we are clarifying the language that is a set of
event sequences of input events, output events, and/or the
internal events. Secondly, we are presenting a identifying way of
equivalence states of a DEVS model in terms of languages traced by
the DEVS model. From the testing way of equivalence states, we can
introduce a way of identifying equivalence DEVSs. This procedure
can be expected to apply the logical analysis step in the whole
design processes.
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